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Technically Speaking, Inc - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc

Zynq All Programmable SoC System Architecture | Online & Onsite - San Diego CA

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$1,400.00

Please note:  This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.

Onsite and Online versions of this course have the exact same material and content. 

Course Description



The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides system architects with the knowledge to effectively architect a Zynq All Programmable SoC. This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq All Programmable SoC project. It covers the architecture of the ARM® CortexTM-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq All Programmable SoC.

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Course Outline

Day 1

  • Zynq All Programmable SoC Overview
  • Inside the Application Processor Unit (APU)
  • Lab 1: Building a Zynq All Programmable SoC Platform
  • Processor Input/Output Peripherals
  • Introduction to AXI
  • Zynq All Programmable SoC PS-PL Interface
  • Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC
  • Zynq All Programmable SoC Booting
  • Lab 3: Using DMA on the Zynq All Programmable SoC

Day 2

  • Zynq All Programmable SoC Memory Resources
  • Meeting Performance Goals
  • Lab 4: Impact of Port Selection on System Performance
  • Zynq All Programmable SoC Hardware Design
  • Zynq All Programmable SoC Software Design
  • Debugging the Zynq All Programmable SoC
  • Lab 5: Debugging on the Zynq All Programmable SoC
  • Zynq All Programmable SoC Tools and Reference Designs
  • Lab 6: Running and Debugging a Linux Application on the Zynq All Programmable SoC

Lab Descriptions

  • Lab 1: Building a Zynq All Programmable SoC Platform Examine the process of using the Vivado IP Integrator tool to create a simple processing system.

  • Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC Connect a programmable logic (PL) design to the embedded processing system (PS).

  • Lab 3: Using DMA on the Zynq All Programmable SoC Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.

  • Lab 4: Impact of Port Selection on System Performance Explore bandwidth issues surrounding the use of the Accelerator Coherency Port (ACP) and the High Performance (HP) ports.

  • Lab 5: Debugging on the Zynq All Programmable SoC Evaluate debugging the hardware and software components of a Zynq All Programmable SoC design.

  • Lab 6: Running and Debugging a Linux Application on the Zynq All Programmable SoC Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)

  • Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC

  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals

  • Analyze the tradeoffs and advantages of performing a function in software versus PL


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