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Technically Speaking, Inc. - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc.

Verilog for Experienced VHDL Users San Diego CA

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$700.00

 

Course Description

Are you a traditional IEEE-1076 VHDL user who must now perform mixed mode synthesis and simulation? This concise 1-day course is designed for hardware designers accustomed to the nuances and syntax requirements of the VHDL language, and needing to perform similar operations using IEEE-1364 Verilog. Most tools today support single kernel VHDL and Verilog module usage, but can you operate effectively in either domain? This specialized course bridges the gap by building upon your existing VHDL skills.

After completing this course, you will have the necessary skills to:

  •  Read existing Verilog HDL code with greater clarity
  • Instantiate Verilog IP Cores into VHDL hierarchy
  • Describe the usage rules and requirement for datatype reg
  • Translate from VHDL process to Verilog procedural blocks
  • Construct a testbench using Verilog syntax
  • Apply any Xilinx XST or Vivado Synthesis Verilog coding specifics
  • Determine when to use Verilog parameters and defines versus VHDL generics and constants
  • Translate from VHDL functions and procedures to Verilog subprograms, tasks and functions
  • Perform basic Verilog File I/O versus VHDL Text I/O operations
  • Create FSMs using Verilog
  • Describe parallels between VHDL variables and Verilog reg datatypes

 

Course Outline

    • Course Introduction: Verilog and VHDL Structural Overview
  • SYNTHESIS
    • Comparing Process and Procedural blocks
    • Data-types and Synthesis Requirements
    • Creating Hierarchy & Design Parameterization
    • Lab 1:
    • RAM & ROM Optimization
    • FSM Coding in Verilog
    • Lab 2:
    • SIMULATION
    • Basic Testbench Structure and Utilization
    • Verilog File I/O Basic Usage
    • Lab 3:
    • Header Files versus Packages/Libraries
    • Xilinx Tool Specific Verilog Usage Recommendations 

    Lab Descriptions

    • Lab 1: Translate existing hierarchical VHDL design into Verilog, and then instantiate Verilog modules into original design
    • Lab 2: Translate FSM into Verilog format and verify in simulation
    • Lab 3: Use Verilog File I/O features to read stimulus input for simulation.

     


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